Recent Changes

Table 3 shows final results with calculated FOMs. The layout simulation has an FOM1 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances.
3 3. Schematic Design Data
specific parameters: the average power,
{EE307_Design_Project_AvgPwr.jpg}
Figure 1 : Complete Circuit Average Power
5 5. Conclusion:
The final FOM1 is 139738 for the non-inverting buffer SPICE design and the 144447 for Electric VLSI SPICE design. The VLSI SPICE design has an FOM2 of 3808164. FOM2 is independent of transistor area and it's cell area is already predefined. Thus to improve FOM2, propagation delay and/or power consumption need to be improved. This holds true for FOM1 as well. Since propagation delay is the largest contributor to FOM (assuming that cell area is predefined), decreasing propagation delay greater than the sum of the increased transistor area and power increase is the easiest and most effective method of improving the FOM. Between the range of 30 - 50 mW power dissipation, small increases in power (<10 mW) decrease can decrease propagation delay by 20-30 ps. This is a worthy trade off. Transistor area is already small (10-20 um^2) and doesn't have a large effect on FOM1. Furthermore, transistor area is difficult to significantly decrease.
methods of analysesanalysis used need
6 6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project

8. Bibliography
0 0. Summary of Results
Final results indicate that the layout simulation has a figure of merit 1 (FOM1) 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances. FOM2 is substantially larger that FOM1 due to being a measurement of the cell area rather than the transistor area. Table 0 shows final results with calculated FOMs. The parameters of the FOM (propagation delay, power dissipation and transistor area) have inverse relationships which are optimized to reduce FOM1 and FOM2.
FOM1
(W/L)n1 (um)
3808164
Table 0 - Design and Layout dimensions, propagation delays, power dissipations, cell areas and FOMs
Final results indicate that the layout simulation has a figure of merit 1 (FOM1) 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances. FOM2 is substantially larger that FOM1 due to being a measurement of the cell area rather than the transistor area. Table 0 shows final results with calculated FOMs. The parameters of the FOM (propagation delay, power dissipation and transistor area) have inverse relationships which are optimized to reduce FOM1 and FOM2.
11. Introduction/Design Specifications:
The project requires the design and layout of a non-inverting CMOS buffer to drive a CMOS inverter. The CMOS buffer must fulfill specific design requirements (Table 1) with a consideration for design tradeoffs: propagation delay, gate power consumption and gate area.

8. Bibliography
0 0. Summary of Results
simulation has ana figure of
FOM1
(W/L)n1 (um)

Tattiana Davenport - tattianad[at]yahoo[dot]com
URLS:
Project Website:
http://team1-ee307w13-icdesign.wikispaces.com/home
VLSI Library:
http://team1-ee307w13-icdesign.wikispaces.com/file/view/EE307W13-Group1.jelib/413747946/EE307W13-Group1.jelib
Table of Contents

Leonardo Alexander Frem - frem.alexander[at]gmail[dot]com
Tattiana Davenport - tattianad[at]yahoo[dot]com
URL:URLS:
Project Website:
http://team1-ee307w13-icdesign.wikispaces.com/home
Electric VLSI Library:
http://team1-ee307w13-icdesign.wikispaces.com/file/view/EE307W13-Group1.jelib/413747946/EE307W13-Group1.jelib
Table of Contents
1.0. Summary of Results
1. Introduction/Design Specifications:Specifications
2. Design Guidelines
3. Schematic Design Data
7. Electric Layout PSpice
8. Bibliography
0.0 0. Summary of relationships which need optimizationare optimized to fully reduce FOM1 and FOM2.
FOM1
(W/L)n1 (um)
5 5. Conclusion:
The final FOM1 is 139738 for the non-inverting buffer SPICE design and the 144447 for Electric VLSI SPICE design. The VLSI SPICE design has an FOM2 of 3808164. FOM2 is independent of transistor area and it's cell area is already predefined. Thus to improve FOM2, propagation delay and/or power consumption need to be improved. This holds true for FOM1 as well. Since propagation delay is the largest contributor to FOM (assuming that cell area is predefined), decreasing propagation delay greater than the sum of the increased transistor area and power increase is the easiest and most effective method of improving the FOM. Between the range of 30 - 50 mW power dissipation, small increases in power (<10 mW) decrease can decrease propagation delay by 20-30 ps. This is a worthy trade off. Transistor area is already small (10-20 um^2) and doesn't have a large effect on FOM1. Furthermore, transistor area is difficult to significantly decrease.
more salient.
6 6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project

Leonardo Alexander Frem - frem.alexander[at]gmail[dot]com
Tattiana Davenport - tattianad[at]yahoo[dot]com
URL:
http://team1-ee307w13-icdesign.wikispaces.com/home
Table of Contents
1. Introduction/Design Specifications:
7. Electric Layout PSpice
8. Bibliography
0. Summary of Results
Final results indicate that the layout simulation has an figure of merit 1 (FOM1) 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances. FOM2 is substantially larger that FOM1 due to being a measurement of the cell area rather than the transistor area. Table 0 shows final results with calculated FOMs. The parameters of the FOM (propagation delay, power dissipation and transistor area) have inverse relationships which need optimization to fully reduce FOM1 and FOM2.
FOM1
(W/L)n1 (um)
(W/L)p1 (um)
(W/L)n2 (um)
(W/L)p2 (um)
Propogation Delay (pS)
Power Dissipation (mW)
Cell Area (um^2)
FOM
Design
(2/0.4)
(8/0.4)
(5/0.4)
(20/0.4)
291
34.3
14
139738.2
Layout
(2/0.4)
(8/0.4)
(5/0.4)
(18/0.4)
310
35.3
13.2
144447.6
FOM2
(2/0.4)
(8/0.4)
(5/0.4)
(18/0.4)
310
35.3
348
3808164
Table 0 - Design and Layout dimensions, propagation delays, power dissipations, cell areas and FOMs
11. Introduction/Design Specifications:
The project requires the design and layout of a non-inverting CMOS buffer to drive a CMOS inverter. The CMOS buffer must fulfill specific design requirements (Table 1) with a consideration for design tradeoffs: propagation delay, gate power consumption and gate area.
The same method of measuring the propagation delays for the schematic design is used for the layout design. Figure 12 shows the tPLH, measured from 50% of the falling edge input voltage to 50% percent of the rising edge output voltage, whereas the tPHL is from the rising edge of the input the falling edge of the output voltage. The propagation delay for the layout design increases by 19 ps over the original design.
5 5. Conclusion:
significantly decrease. The
The final buffer FOM parameters. Another, more doable step, to improving the FOM is to create a SPICE simulation to determine the gate capacitance of the final inverter. This information makes the data in Table 1 more salient.
6 6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project

2. Mary Jane Irwin & Vijay Narayanan, CSE477 VLSI Digital Circuits Fall 2003, Lecture Slides, [Online]. Available:http://www.cse.psu.edu/research/mdl/mji/mjicourses/477/cse477-11speed.ppt/,
Adapted from J. Rabaey, A. Chandrakasan, & B. Nikolic, Digital Integrated Circuits, Second Ed., 2003, Prentice Hall.
3. Jim Stiles, CMOS Propagation Delay, Lecture Document, [Online].
Available: http://www.ittc.ku.edu/~jstiles/312/handouts/CMOS%20Propagation%20Delay.pdf
In figure

2.1 Figure of Merit & Final Results
Figure of merit (FOM) is a design guideline used to optimize the buffer design. It is not the only consideration when designing a buffer but it is a good benchmark to follow. The optimized FOM is the lowest possible value that still follows the CMOS buffer design specifications. The FOM1 is determined for both the initial design and the layout. FOM2 is only calculated for the layout because the initial design does not consider cell area. In a production environment FOM2 is a more salient measurement because it the cell area determines how many buffers can be included on an integrated circuit. FOMs are defined as follows:
transistor area (μm^2)FOM2(μm^2)
FOM2 = propagation
FOM1
(W/L)n1 (um)
{EE307_Design_Project_PropDelayEq.jpg}
{EE307_Design_Project_PropDelay10MHz.jpg} Figure 3 : Transient Response of CMOS Buffer for 10 MHz
remeasuring the propogationpropagation delay validates waveform is infactin fact the true
{EE307_Design_Project_PropDelay10MHz_PLH.jpg} Figure 4: Propagation Delay (Low-High) for 10 MHz
{EE307_Design_Project_PropDelay10MHz_PHL.jpg} Figure 5: Propagation Delay (High-Low) for 10 MHz
{electricDesign.jpg} Figure 8: Non-inverting buffer schematic
{CMOSdesign.jpg} Figure 9: Non-inverting buffer design layout using Electric
generating SPICE netlistsnetlist for circuit
{designpower.jpg} Figure 10 - Power dissipation of layout design
Figure 11 displays the voltage transfer characteristic of the layout design of the non-inverting buffer. The output high and low voltages are still 5 V and 0 V, respectively, matching the schematic design. Taking the derivative of the output results in an input high voltage of 3.0179 V and an input low voltage of 2.776 V.
The same method of measuring the propagation delays for the schematic design is used for the layout design. Figure 12 shows the tPLH, measured from 50% of the falling edge input voltage to 50% percent of the rising edge output voltage, whereas the tPHL is from the rising edge of the input the falling edge of the output voltage. The propagation delay for the layout design increases by 19 ps over the original design.
5 5. Conclusion:
significantly decrease. The final buffer area was determined to be a good fit because the propagation delay decreased proportionally with FOM while power dissipation increase did not exceed the prop delay decrease. For the "best fit", the methods of analyses used need to be improved. This requires a deeper understanding of the phenomenology and perhaps simulation tools that can run sweeps of different configurations and automatically calculate FOM parameters.
6 6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project

{designpropdelay.jpg}
Figure 12 - propagation delay of layout design
PropagationThe same method of measuring the propagation delays for the schematic design is used for the layout design. Figure 12 shows the tPLH, measured from 50% of the falling edge input voltage to 50% percent of the rising edge output voltage, whereas the tPHL is from the rising edge of the input the falling edge of the output voltage. The propagation delay for the layout design increases by
5 5. Conclusion:
The final FOM1 is 139738 for the non-inverting buffer SPICE design and the 144447 for Electric VLSI SPICE design. The VLSI SPICE design has an FOM2 of 3808164. FOM2 is independent of transistor area and it's cell area is already predefined. Thus to improve FOM2, propagation delay and/or power consumption need to be improved. This holds true for FOM1 as well. Since propagation delay is the largest contributor to FOM (assuming that cell area is predefined), decreasing propagation delay greater than the sum of the increased transistor area and power increase is the easiest and most effective method of improving the FOM. Between the range of 30 - 50 mW power dissipation, small increases in power (<10 mW) decrease can decrease propagation delay by 20-30 ps. This is a worthy trade off. Transistor area is already small (10-20 um^2) and doesn't have a large effect on FOM1. Furthermore, transistor area is difficult to significantly decrease.
***********************************************************************************************
.END
Electric Layout PSpice Code:PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project
*** -- http://team1-ee307w13-icdesign.wikispaces.com/ --