Table 0 - Design and Layout dimensions, propagation delays, power dissipations, cell areas and FOMs
Final results indicate that the layout simulation has a figure of merit 1 (FOM1) 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances. FOM2 is substantially larger that FOM1 due to being a measurement of the cell area rather than the transistor area. Table 0 shows final results with calculated FOMs. The parameters of the FOM (propagation delay, power dissipation and transistor area) have inverse relationships which are optimized to reduce FOM1 and FOM2.
1. Introduction/Design Specifications:
The project requires the design and layout of a non-inverting CMOS buffer to drive a CMOS inverter. The CMOS buffer must fulfill specific design requirements (Table 1) with a consideration for design tradeoffs: propagation delay, gate power consumption and gate area.
Inverting and non-inverting buffers are used to drive circuits with augmented currents to maintain specified noise margins and/or swing the voltage rail-to-rail. Like in the situation of the provided CMOS inverter, the voltage source does not drive sufficient current to charge the load capacitor quickly enough for the voltages to reach specified levels. A cascade of buffers with increasing gate sizes steps up the systems current gradually while overcoming each successive gate capacitance.
There are analytical "rules of thumb" that are employed in the design of the gates' channel lengths but there are also practical layout concerns, like layout area, that define the constraints of the final circuit. A good design will rectify discrepancies between the design and layout as closely as possible.
CMOS Buffer Design Specifications
Vin [Vpp]
5
Frequency [GHz]
1
Noise Margins [V]
>= .5
Signal Type
Square
Transistor Area [μm]
<= 100
Gate length [μm]
>= .400
Table 1 - CMOS Buffer Design Specifications
2. Design Guidelines
Equation f = (Cl/Cg)^(1/n) determines the ratio of sizes of the cascading gate areas where Cl is load capacitance, Cg is gate capacitance of the final inverter and n is the number of inverting buffer. Table 2 shows fanout values for different gate sizes. An assumption is made that the gate capacitance is smaller than the load capacitance by at least a factor of 10. The propagation delay is determined by tp = tpo * (1 + f/gamma) where the average of the PMOS and NMOS gamma is ~0.5 and tpo is the intrinsic delay of an inverter. Thus an increase in buffer inverter areas, by a factor of 3 or 4, does not increase the propagation delay significantly. If f is greater than 5 the designer needs to begin thinking about using four inverting buffers, rather than two, to step up the gate sizes.
n (# of inverting buffers)
2
Cl(pF)
1.20E+00
f (fanout)
Cg (pF)
34.64
1.E-03
10.95
1.E-02
3.46
1.E-01
1.10
1.E+00
0.35
1.E+01
0.11
1.E+02
0.03
1.E+03
0.01
1.E+04
Table 2 - Fanout for varying gate capacitances
For a CMOS gate the proportion of PMOS and NMOS gate areas should roughly equal the proportion of the Kn to Kp to foster symmetric switching. NMOS doped transistors conduct current more readily than PMOS doped transistors. Since Kn is 4x greater than Kp, the channel length area (W*L)p = 4(W*L)n for Kn = 6.5E-4 and Kp = 1.62 E-4.
Figure of Merit & Final Results Figure of merit (FOM) is a design guideline used to optimize the buffer design. It is not the only consideration when designing a buffer but it is a good benchmark to follow. The optimized FOM is the lowest possible value that still follows the CMOS buffer design specifications. The FOM1 is determined for both the initial design and the layout. FOM2 is only calculated for the layout because the initial design does not consider cell area. In a production environment FOM2 is a more salient measurement because it the cell area determines how many buffers can be included on an integrated circuit. FOMs are defined as follows: FOM1 = propagation delay (ps) * power dissipation (mW) * transistor area (μm^2) FOM2 = propagation delay (ps) * power dissipation (mW) * buffer cell area (μm^2)
FOM1
(W/L)n1 (um)
(W/L)p1 (um)
(W/L)n2 (um)
(W/L)p2 (um)
Propogation Delay (pS)
Power Dissipation (mW)
Cell Area (um^2)
FOM
Design
(2/0.4)
(8/0.4)
(5/0.4)
(20/0.4)
291
34.3
14
139738.2
Layout
(2/0.4)
(8/0.4)
(5/0.4)
(18/0.4)
310
35.3
13.2
144447.6
FOM2
(2/0.4)
(8/0.4)
(5/0.4)
(18/0.4)
310
35.3
348
3808164
Table 3 - Design and Layout dimensions, propagation delays, power dissipations, cell areas and FOMs
Table 3 shows final results with calculated FOMs. The layout simulation has an FOM1 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances.
3. Schematic Design Data
The initial design of the CMOS buffer with the inverting load was simulated using OrCAD PSpice to collect the specific parameters: average power, propagation delay and noise margins.
Figure 1 : Complete Circuit Average Power
Figure 1 shows the average power dissipation through the CMOS buffer and inverting load. The magnitude of the power of the complete circuit is 34.323 mW.
Figure 2 : Transient Response and Propagation Delays on CMOS Buffer for 1 GHz
Figure 2 shows the transient response of the circuit. Measuring the difference between input voltage and output voltage yields a tPLH and tPHL. To find the propagation delay of low to high of the output signal, tPLH, the change in time between the fall of the input and the rise of the output is measured at the following voltage level:
Using the same voltage level, the change in time is calculated between the rise of the input and the fall of the output, to find the propagation delay from high to low, tPHL, of the output signal. The average of these two values is the propagation delay, which in this case is 291.294 ps. To derive this value the following equation is used:
Figure 3 : Transient Response of CMOS Buffer for 10 MHz
Figure 3, 4 and 5 verify that the calculated propagation delay is valid. Reducing the system frequency from 1 GHz to 10 MHz and remeasuring the propagation delay validates the delay measured on the GHz waveform is in fact the true value. The propagation delay is remeasured at 291 ps, resulting in a small error of 0.101% due to insufficient significant figures from the 10 MHz clock. Figure 3 shows the 10 MHz waveform. Figure 4 and 5 zoom in on the waveform to respectively measure tPLH and tPHL.
Figure 4: Propagation Delay (Low-High) for 10 MHz
Figure 5: Propagation Delay (High-Low) for 10 MHz
Figure 6 and 7 display the voltage transfer characteristic of the CMOS buffer. The rail is pulled up to 5 V by the PMOS transistors and the ground is pulled down to 0 V by the NMOS, making VOH = 5 V and VOL = 0 V. The derivative of the output voltage of the buffer is shown to calculate noise margin to calculate the noise margins. VIL = 2.77 V and VIH = 3.01 V when dVIN/dVIN_IN = 1.
Figure 6 : Voltage Transfer Characteristic and Output Voltage Derivation of CMOS Buffer
Figure 7 : Low-High Input Voltages of CMOS Buffer
The noise margins are calculate with the following equations:
These values fall well within the specification that the noise margins be greater than 0.5 V.
4. Design Layout
Figure 8 displays the non-inverting buffer schematic. Figure 9 displays that same buffer's layout using Electric VLSI design system. PMOS2 had to be reduced from 20 um to 18 um to fit within the design area specifications. Otherwise, there is ample area within the non-inverting buffer. The link below provides the Electric VLSI design system file:
Figure 9: Non-inverting buffer design layout using Electric
The Electric VLSI design tool is capable of generating SPICE netlist for circuit analysis. Figure 10 shows the waveform of the average power and was measured to be 35.29 mW. This is a 1 mW increase in power from the original circuit design.
Figure 10 - Power dissipation of layout design
Figure 11 displays the voltage transfer characteristic of the layout design of the non-inverting buffer. The output high and low voltages are still 5 V and 0 V, respectively, matching the schematic design. Taking the derivative of the output results in an input high voltage of 3.0179 V and an input low voltage of 2.776 V.
Figure 11 - voltage transfer characteristic of layout design
Using those values the noise margins are calculated (same from the schematic calculations):
Those noise margins are well above the 0.5 V specification. The low noise margin came in with a 0.21% error from the schematic margin voltage and the high noise margin with a 0.40% error. With errors this low, they are negligible.
Figure 12 - propagation delay of layout design
The same method of measuring the propagation delays for the schematic design is used for the layout design. Figure 12 shows the tPLH, measured from 50% of the falling edge input voltage to 50% percent of the rising edge output voltage, whereas the tPHL is from the rising edge of the input the falling edge of the output voltage. The propagation delay for the layout design increases by 19 ps over the original design.
5. Conclusion:
The final FOM1 is 139738 for the non-inverting buffer SPICE design and the 144447 for Electric VLSI SPICE design. The VLSI SPICE design has an FOM2 of 3808164. FOM2 is independent of transistor area and it's cell area is already predefined. Thus to improve FOM2, propagation delay and/or power consumption need to be improved. This holds true for FOM1 as well. Since propagation delay is the largest contributor to FOM (assuming that cell area is predefined), decreasing propagation delay greater than the sum of the increased transistor area and power increase is the easiest and most effective method of improving the FOM. Between the range of 30 - 50 mW power dissipation, small increases in power (<10 mW) decrease can decrease propagation delay by 20-30 ps. This is a worthy trade off. Transistor area is already small (10-20 um^2) and doesn't have a large effect on FOM1. Furthermore, transistor area is difficult to significantly decrease.
The final buffer area was determined to be a good fit because the propagation delay decreased proportionally with FOM while power dissipation increase did not exceed the prop delay decrease. For the "best fit", the methods of analysis used need to be improved. This requires a deeper understanding of the phenomenology and perhaps simulation tools that can run sweeps of different configurations and automatically calculate FOM parameters. Another, more doable step, to improving the FOM is to create a SPICE simulation to determine the gate capacitance of the final inverter. This information makes the data in Table 1 more salient.
6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project *** -- http://team1-ee307w13-icdesign.wikispaces.com/ -- *** Kamron Sockolov *** Leonardo Alexander Frem *** Tattiana Davenport
*** SPICE deck for cell EmptyBufWLoad{lay} from library EE307W09
*** Created on Sat Jan 03, 2009 14:44:17
*** Last revised on Thu Dec 30, 2010 14:08:04
*** Written on Tue Jan 13, 2009 22:36:44 by Electric VLSI Design System,
*version 8.08
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** N-Active:areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq
***
*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um, res=6.2ohms/sq
*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq
*** Transistor-Poly: areacap=0.09FF/um^2,edgecap=0.0FF/um, res=2.5ohms/sq
*** Poly-Cut:areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq
*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um, res=0.078ohms/sq
*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq
*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** SPICE deck for cell EmptyBufWLoad{lay} from library EE307W13
*** Created on Sat Jan 03, 2009 14:44:17
*** Last revised on Sat Jan 12, 2013 17:22:16
*** Written on Tue Jan 13, 2009 22:36:44 by Electric VLSI Design System,
*version 8.08
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** N-Active:areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq
***
*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um, res=6.2ohms/sq
*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq
*** Transistor-Poly: areacap=0.09FF/um^2,edgecap=0.0FF/um, res=2.5ohms/sq
*** Poly-Cut:areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq
*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um, res=0.078ohms/sq
*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq
*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via4: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-5: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via5: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-6: areacap=0.0423FF/um^2, edgecap=0.1273FF/um, res=0.036ohms/sq
*.OPTIONS NOMOD NOPAGE
*** CELL: EE307W13:EmptyBuffer{lay}
.SUBCKT EmptyBuffer In Out gnd vdd
** Extracted Parasitic Capacitors ***
MN1 3 In gnd gnd CMOSN L=0.4u W=2u
*L=0.4u W=2.64u
MP1 3 In vdd vdd CMOSP L=0.4u W=8u
*L=0.4u W=10.56u
MN2 Out 3 gnd gnd CMOSN L=0.4uW=5u
*L=0.4u W=5.26u
MP2 Out 3 vdd vdd CMOSP L=0.4u W=20u
*L=0.4u W=21.12u
* D G S B
*
* Electric didn't produce the code between *1 and *2
* Braun added it as an example
*2
*** TOP LEVEL CELL: EmptyBufWLoad{lay}
XBufOut In Out 0 vdd InvLoad
XIn In_In In 0 vdd EmptyBuffer
** Extracted Parasitic Capacitors ***
C0 In 0 0.411fF
** Extracted Parasitic Resistors ***
*******************************************************************************************
* *
* The above circuit file results after substituting *
* "_" for "#" *
* "-" for "@" *
* NMOS model name "CMOSN" for "N" *
* PMOS model name "CMOSP" for "P" *
* *
* In the TOP LEVEL CELL, substitute node "0" for "gnd" *
* *
* The above file also comments out the ".OPTIONS NOMOD NOPAGE" line *
* *
* Electric didn't produce the rest of the file *
* *
* Remember to add the transistor models and load capacitance Cout *
********************************************************************************************
EE 307-03, Winter 2013, CMOS Buffer Design & Layout Project
Team 1:
Kamron Sockolov - kamron.sockolov[at]gmail[dot]comLeonardo Alexander Frem - frem.alexander[at]gmail[dot]com
Tattiana Davenport - tattianad[at]yahoo[dot]com
URLS:
Project Website:http://team1-ee307w13-icdesign.wikispaces.com/home
Electric VLSI Library:
http://team1-ee307w13-icdesign.wikispaces.com/file/view/EE307W13-Group1.jelib/413747946/EE307W13-Group1.jelib
Table of Contents
0. Summary of Results1. Introduction/Design Specifications
2. Design Guidelines
3. Schematic Design Data
4. Design Layout
5. Conclusion
6. Schematic Design PSpice
7. Electric Layout PSpice
8. Bibliography
0. Summary of Results
Final results indicate that the layout simulation has a figure of merit 1 (FOM1) 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances. FOM2 is substantially larger that FOM1 due to being a measurement of the cell area rather than the transistor area. Table 0 shows final results with calculated FOMs. The parameters of the FOM (propagation delay, power dissipation and transistor area) have inverse relationships which are optimized to reduce FOM1 and FOM2.
1. Introduction/Design Specifications:
The project requires the design and layout of a non-inverting CMOS buffer to drive a CMOS inverter. The CMOS buffer must fulfill specific design requirements (Table 1) with a consideration for design tradeoffs: propagation delay, gate power consumption and gate area.
Inverting and non-inverting buffers are used to drive circuits with augmented currents to maintain specified noise margins and/or swing the voltage rail-to-rail. Like in the situation of the provided CMOS inverter, the voltage source does not drive sufficient current to charge the load capacitor quickly enough for the voltages to reach specified levels. A cascade of buffers with increasing gate sizes steps up the systems current gradually while overcoming each successive gate capacitance.
There are analytical "rules of thumb" that are employed in the design of the gates' channel lengths but there are also practical layout concerns, like layout area, that define the constraints of the final circuit. A good design will rectify discrepancies between the design and layout as closely as possible.
2. Design Guidelines
Equation f = (Cl/Cg)^(1/n) determines the ratio of sizes of the cascading gate areas where Cl is load capacitance, Cg is gate capacitance of the final inverter and n is the number of inverting buffer. Table 2 shows fanout values for different gate sizes. An assumption is made that the gate capacitance is smaller than the load capacitance by at least a factor of 10. The propagation delay is determined by tp = tpo * (1 + f/gamma) where the average of the PMOS and NMOS gamma is ~0.5 and tpo is the intrinsic delay of an inverter. Thus an increase in buffer inverter areas, by a factor of 3 or 4, does not increase the propagation delay significantly. If f is greater than 5 the designer needs to begin thinking about using four inverting buffers, rather than two, to step up the gate sizes.
For a CMOS gate the proportion of PMOS and NMOS gate areas should roughly equal the proportion of the Kn to Kp to foster symmetric switching. NMOS doped transistors conduct current more readily than PMOS doped transistors. Since Kn is 4x greater than Kp, the channel length area (W*L)p = 4(W*L)n for Kn = 6.5E-4 and Kp = 1.62 E-4.
Figure of Merit & Final Results
Figure of merit (FOM) is a design guideline used to optimize the buffer design. It is not the only consideration when designing a buffer but it is a good benchmark to follow. The optimized FOM is the lowest possible value that still follows the CMOS buffer design specifications. The FOM1 is determined for both the initial design and the layout. FOM2 is only calculated for the layout because the initial design does not consider cell area. In a production environment FOM2 is a more salient measurement because it the cell area determines how many buffers can be included on an integrated circuit. FOMs are defined as follows:
FOM1 = propagation delay (ps) * power dissipation (mW) * transistor area (μm^2)
FOM2 = propagation delay (ps) * power dissipation (mW) * buffer cell area (μm^2)
Table 3 shows final results with calculated FOMs. The layout simulation has an FOM1 4709 greater than the design simulation FOM1. To make the layout fit the area is reduced by 6% which increases the propagation delay by 6.5%. Furthermore, the layout introduces parasitic capacitances and resistances.
3. Schematic Design Data
The initial design of the CMOS buffer with the inverting load was simulated using OrCAD PSpice to collect the specific parameters: average power, propagation delay and noise margins.
Figure 1 : Complete Circuit Average Power
Figure 1 shows the average power dissipation through the CMOS buffer and inverting load. The magnitude of the power of the complete circuit is 34.323 mW.
Figure 2 shows the transient response of the circuit. Measuring the difference between input voltage and output voltage yields a tPLH and tPHL. To find the propagation delay of low to high of the output signal, tPLH, the change in time between the fall of the input and the rise of the output is measured at the following voltage level:
Figure 3, 4 and 5 verify that the calculated propagation delay is valid. Reducing the system frequency from 1 GHz to 10 MHz and remeasuring the propagation delay validates the delay measured on the GHz waveform is in fact the true value. The propagation delay is remeasured at 291 ps, resulting in a small error of 0.101% due to insufficient significant figures from the 10 MHz clock. Figure 3 shows the 10 MHz waveform. Figure 4 and 5 zoom in on the waveform to respectively measure tPLH and tPHL.
Figure 6 and 7 display the voltage transfer characteristic of the CMOS buffer. The rail is pulled up to 5 V by the PMOS transistors and the ground is pulled down to 0 V by the NMOS, making VOH = 5 V and VOL = 0 V. The derivative of the output voltage of the buffer is shown to calculate noise margin to calculate the noise margins. VIL = 2.77 V and VIH = 3.01 V when dVIN/dVIN_IN = 1.
The noise margins are calculate with the following equations:
These values fall well within the specification that the noise margins be greater than 0.5 V.
4. Design Layout
Figure 8 displays the non-inverting buffer schematic. Figure 9 displays that same buffer's layout using Electric VLSI design system. PMOS2 had to be reduced from 20 um to 18 um to fit within the design area specifications. Otherwise, there is ample area within the non-inverting buffer. The link below provides the Electric VLSI design system file:
The Electric VLSI design tool is capable of generating SPICE netlist for circuit analysis. Figure 10 shows the waveform of the average power and was measured to be 35.29 mW. This is a 1 mW increase in power from the original circuit design.
Figure 11 displays the voltage transfer characteristic of the layout design of the non-inverting buffer. The output high and low voltages are still 5 V and 0 V, respectively, matching the schematic design. Taking the derivative of the output results in an input high voltage of 3.0179 V and an input low voltage of 2.776 V.
Using those values the noise margins are calculated (same from the schematic calculations):
Figure 12 - propagation delay of layout design
The same method of measuring the propagation delays for the schematic design is used for the layout design. Figure 12 shows the tPLH, measured from 50% of the falling edge input voltage to 50% percent of the rising edge output voltage, whereas the tPHL is from the rising edge of the input the falling edge of the output voltage. The propagation delay for the layout design increases by 19 ps over the original design.
5. Conclusion:
The final FOM1 is 139738 for the non-inverting buffer SPICE design and the 144447 for Electric VLSI SPICE design. The VLSI SPICE design has an FOM2 of 3808164. FOM2 is independent of transistor area and it's cell area is already predefined. Thus to improve FOM2, propagation delay and/or power consumption need to be improved. This holds true for FOM1 as well. Since propagation delay is the largest contributor to FOM (assuming that cell area is predefined), decreasing propagation delay greater than the sum of the increased transistor area and power increase is the easiest and most effective method of improving the FOM. Between the range of 30 - 50 mW power dissipation, small increases in power (<10 mW) decrease can decrease propagation delay by 20-30 ps. This is a worthy trade off. Transistor area is already small (10-20 um^2) and doesn't have a large effect on FOM1. Furthermore, transistor area is difficult to significantly decrease.
The final buffer area was determined to be a good fit because the propagation delay decreased proportionally with FOM while power dissipation increase did not exceed the prop delay decrease. For the "best fit", the methods of analysis used need to be improved. This requires a deeper understanding of the phenomenology and perhaps simulation tools that can run sweeps of different configurations and automatically calculate FOM parameters. Another, more doable step, to improving the FOM is to create a SPICE simulation to determine the gate capacitance of the final inverter. This information makes the data in Table 1 more salient.
6. Schematic Design PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project*** -- http://team1-ee307w13-icdesign.wikispaces.com/ --
*** Kamron Sockolov
*** Leonardo Alexander Frem
*** Tattiana Davenport
*** SPICE deck for cell EmptyBufWLoad{lay} from library EE307W09
*** Created on Sat Jan 03, 2009 14:44:17
*** Last revised on Thu Dec 30, 2010 14:08:04
*** Written on Tue Jan 13, 2009 22:36:44 by Electric VLSI Design System,
*version 8.08
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** N-Active:areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq
***
*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um, res=6.2ohms/sq
*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq
*** Transistor-Poly: areacap=0.09FF/um^2,edgecap=0.0FF/um, res=2.5ohms/sq
*** Poly-Cut:areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq
*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um, res=0.078ohms/sq
*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq
*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** SPICE deck for cell EmptyBufWLoad{lay} from library EE307W13
*** Created on Sat Jan 03, 2009 14:44:17
*** Last revised on Sat Jan 12, 2013 17:22:16
*** Written on Tue Jan 13, 2009 22:36:44 by Electric VLSI Design System,
*version 8.08
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** N-Active:areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq
***
*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um, res=6.2ohms/sq
*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq
*** Transistor-Poly: areacap=0.09FF/um^2,edgecap=0.0FF/um, res=2.5ohms/sq
*** Poly-Cut:areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq
*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um, res=0.078ohms/sq
*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq
*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via4: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-5: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq
*** Via5: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-6: areacap=0.0423FF/um^2, edgecap=0.1273FF/um, res=0.036ohms/sq
*.OPTIONS NOMOD NOPAGE
*** CELL: EE307W13:EmptyBuffer{lay}
.SUBCKT EmptyBuffer In Out gnd vdd
** Extracted Parasitic Capacitors ***
MN1 3 In gnd gnd CMOSN L=0.4u W=2u
*L=0.4u W=2.64u
MP1 3 In vdd vdd CMOSP L=0.4u W=8u
*L=0.4u W=10.56u
MN2 Out 3 gnd gnd CMOSN L=0.4uW=5u
*L=0.4u W=5.26u
MP2 Out 3 vdd vdd CMOSP L=0.4u W=20u
*L=0.4u W=21.12u
* D G S B
*
* Electric didn't produce the code between *1 and *2
* Braun added it as an example
*2
** Extracted Parasitic Resistors ***
.ENDS EmptyBuffer
*** CELL: EE307W13:InvLoad{lay}
.SUBCKT InvLoad In Out gnd vdd
Mnmos-10 gnd In_1nmos-10_n-trans-poly-left Out gnd CMOSN L=0.4U W=0.8U AS=1.4P
+AD=2.32P PS=5U PD=8.8U
Mpmos-5 Out In_2pmos-5_p-trans-poly-right vdd vdd CMOSP L=0.4U W=0.8U AS=2.9P
+AD=1.4P PS=11U PD=5U
** Extracted Parasitic Capacitors ***
C0 Out 0 3.667fF
C1 In 0 1.039fF
** Extracted Parasitic Resistors ***
R0 In_1nmos-10_n-trans-poly-left In_1nmos-10_n-trans-poly-left__0 9.3
R1 In_1nmos-10_n-trans-poly-left__0 In_1nmos-10_n-trans-poly-left__1 9.3
R2 In_1nmos-10_n-trans-poly-left__1 In_1nmos-10_n-trans-poly-left__2 9.3
R3 In_1nmos-10_n-trans-poly-left__2 In_1nmos-10_n-trans-poly-left__3 9.3
R4 In_1nmos-10_n-trans-poly-left__3 In 9.3
R5 In In__0 9.817
R6 In__0 In__1 9.817
R7 In__1 In__2 9.817
R8 In__2 In__3 9.817
R9 In__3 In__4 9.817
R10 In__4 In_2pmos-5_p-trans-poly-right 9.817
.ENDS InvLoad
*** TOP LEVEL CELL: EmptyBufWLoad{lay}
XBufOut In Out 0 vdd InvLoad
XIn In_In In 0 vdd EmptyBuffer
** Extracted Parasitic Capacitors ***
C0 In 0 0.411fF
** Extracted Parasitic Resistors ***
*******************************************************************************************
* *
* The above circuit file results after substituting *
* "_" for "#" *
* "-" for "@" *
* NMOS model name "CMOSN" for "N" *
* PMOS model name "CMOSP" for "P" *
* *
* In the TOP LEVEL CELL, substitute node "0" for "gnd" *
* *
* The above file also comments out the ".OPTIONS NOMOD NOPAGE" line *
* *
* Electric didn't produce the rest of the file *
* *
* Remember to add the transistor models and load capacitance Cout *
********************************************************************************************
Cout In 0 1.2p
Vdd vdd 0 5
Vin In_In 0 PULSE (0 5 0 5p 5p 49.5n .1u)
*.DC Vin 0 5 0.01
.TRAN .1n .5u 0 .1n
.PROBE
.OP
***********************************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
***********************************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.442 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 6.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.542 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 1.619415E-4 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
***********************************************************************************************
.END
7. Electric Layout PSpice:
*** Winter 2013, Team 1, CMOS Buffer Design & Layout Project*** -- http://team1-ee307w13-icdesign.wikispaces.com/ --
*** Kamron Sockolov
*** Leonardo Alexander Frem
*** Tattiana Davenport
*** SPICE deck for cell BufWLoad{lay} from library EE307W13-Group1-Ver2
*** Created on Tue Jan 13, 2009 23:36:02
*** Last revised on Wed Jan 14, 2009 21:33:11
*** Written on Sun Mar 10, 2013 16:27:53 by Electric VLSI Design System,
*version 9.03
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** N-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq
***
*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um,res=6.2ohms/sq
*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq
*** Transistor-Poly: areacap=0.09FF/um^2,edgecap=0.0FF/um, res=2.5ohms/sq
*** Poly-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq
*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq
*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um,res=0.078ohms/sq
*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um,res=0.078ohms/sq
*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq
*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um,res=0.078ohms/sq
*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um,res=0.078ohms/sq
*** Via4: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-5: areacap=0.0843FF/um^2, edgecap=0.0974FF/um,res=0.078ohms/sq
*** Via5: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq
*** Metal-6: areacap=0.0423FF/um^2, edgecap=0.1273FF/um,res=0.036ohms/sq
*** Hi-Res: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq
*** SUBCIRCUIT InvLoad FROM CELL InvLoad{lay}
.SUBCKT InvLoad In Out gnd vdd
Mnmos-10 gnd In-1nmos-10_poly-left Out gnd CMOSN L=0.4U W=0.8U AS=1.4P AD=2.32P
+PS=5U PD=8.8U
Mpmos-5 Out In-2pmos-5_poly-right vdd vdd CMOSP L=0.4U W=0.8U AS=2.9P AD=1.4P
+PS=11U PD=5U
** Extracted Parasitic Capacitors ***
C0 Out 0 3.667fF
C1 In 0 1.039fF
** Extracted Parasitic Resistors ***
R0 In-1nmos-10_poly-left In-1nmos-10_poly-left--0 9.3
R1 In-1nmos-10_poly-left--0 In-1nmos-10_poly-left--1 9.3
R2 In-1nmos-10_poly-left--1 In-1nmos-10_poly-left--2 9.3
R3 In-1nmos-10_poly-left--2 In-1nmos-10_poly-left--3 9.3
R4 In-1nmos-10_poly-left--3 In 9.3
R5 In In--0 9.817
R6 In--0 In--1 9.817
R7 In--1 In--2 9.817
R8 In--2 In--3 9.817
R9 In--3 In--4 9.817
R10 In--4 In-2pmos-5_poly-right 9.817
.ENDS InvLoad
*** SUBCIRCUIT Buffer FROM CELL Buffer{lay}
.SUBCKT Buffer In Out gnd vdd
Mnmos-0 gnd In-1nmos-0_poly-left net-346 gnd CMOSN L=0.4U W=2U AS=3.6P AD=3.1P
+PS=12.4U PD=11.2U
Mnmos-1 gnd net-346-11nmos-1_poly-left Out gnd CMOSN L=0.4U W=5U AS=7.88P AD=3.1P
+PS=26.8U PD=11.2U
Mpmos-1 net-346 In-2pmos-1_poly-left vdd vdd CMOSP L=0.4U W=8U AS=8.85P AD=3.6P
+PS=30.3U PD=12.4U
Mpmos-2 vdd net-346-5pmos-2_poly-left Out vdd CMOSP L=0.4U W=18U AS=7.88P
+AD=8.85P PS=26.8U PD=30.3U
** Extracted Parasitic Capacitors ***
C0 In 0 0.735fF
C1 net-346 0 4.38fF
C2 Out 0 3.81fF
C3 In-3pin-80_polysilicon-1 0 0.354fF
C4 net-346-6pin-87_polysilicon-1 0 0.152fF
C5 net-346-9pin-89_polysilicon-1 0 0.184fF
C6 net-346-10pin-92_polysilicon-1 0 0.16fF
C7 net-346-13pin-94_polysilicon-1 0 0.117fF
C8 net-346-14pin-96_polysilicon-1 0 0.161fF
C9 net-346-15pin-97_polysilicon-1 0 0.202fF
** Extracted Parasitic Resistors ***
R0 In-1nmos-0_poly-left In 9.3
R1 In-2pmos-1_poly-left In-3pin-80_polysilicon-1 6.2
R2 In In--0 8.308
C10 In--0 0 0.3fF
R3 In--0 In--1 8.308
C11 In--1 0 0.3fF
R4 In--1 In--2 8.308
C12 In--2 0 0.3fF
R5 In--2 In--3 8.308
C13 In--3 0 0.3fF
R6 In--3 In-3pin-80_polysilicon-1 8.308
R7 net-346-5pmos-2_poly-left net-346-5pmos-2_poly-left--0 8.138
R8 net-346-5pmos-2_poly-left--0 net-346-5pmos-2_poly-left--1 8.138
R9 net-346-5pmos-2_poly-left--1 net-346-5pmos-2_poly-left--2 8.138
R10 net-346-5pmos-2_poly-left--2 net-346-6pin-87_polysilicon-1 8.138
R11 net-346-9pin-89_polysilicon-1 net-346-9pin-89_polysilicon-1--0 8.68
R12 net-346-9pin-89_polysilicon-1--0 net-346-9pin-89_polysilicon-1--1 8.68
R13 net-346-9pin-89_polysilicon-1--1 net-346-9pin-89_polysilicon-1--2 8.68
R14 net-346-9pin-89_polysilicon-1--2 net-346-9pin-89_polysilicon-1--3 8.68
R15 net-346-9pin-89_polysilicon-1--3 net-346-10pin-92_polysilicon-1 8.68
R16 net-346-10pin-92_polysilicon-1 net-346-10pin-92_polysilicon-1--0 8.138
R17 net-346-10pin-92_polysilicon-1--0 net-346-10pin-92_polysilicon-1--1 8.138
R18 net-346-10pin-92_polysilicon-1--1 net-346-10pin-92_polysilicon-1--2 8.138
R19 net-346-10pin-92_polysilicon-1--2 net-346 8.138
R20 net-346-11nmos-1_poly-left net-346-11nmos-1_poly-left--0 6.975
R21 net-346-11nmos-1_poly-left--0 net-346-12pin-93_polysilicon-1 6.975
R22 net-346-12pin-93_polysilicon-1 net-346-13pin-94_polysilicon-1 6.2
R23 net-346-13pin-94_polysilicon-1 net-346-13pin-94_polysilicon-1--0 8.37
R24 net-346-13pin-94_polysilicon-1--0 net-346-13pin-94_polysilicon-1--1 8.37
R25 net-346-13pin-94_polysilicon-1--1 net-346-13pin-94_polysilicon-1--2 8.37
R26 net-346-13pin-94_polysilicon-1--2 net-346-13pin-94_polysilicon-1--3 8.37
R27 net-346-13pin-94_polysilicon-1--3 net-346 8.37
R28 net-346-6pin-87_polysilicon-1 net-346-6pin-87_polysilicon-1--0 8.783
R29 net-346-6pin-87_polysilicon-1--0 net-346-6pin-87_polysilicon-1--1 8.783
R30 net-346-6pin-87_polysilicon-1--1 net-346-14pin-96_polysilicon-1 8.783
R31 net-346-14pin-96_polysilicon-1 net-346-14pin-96_polysilicon-1--0 8.68
R32 net-346-14pin-96_polysilicon-1--0 net-346-14pin-96_polysilicon-1--1 8.68
R33 net-346-14pin-96_polysilicon-1--1 net-346-14pin-96_polysilicon-1--2 8.68
R34 net-346-14pin-96_polysilicon-1--2 net-346-14pin-96_polysilicon-1--3 8.68
R35 net-346-14pin-96_polysilicon-1--3 net-346-15pin-97_polysilicon-1 8.68
R36 net-346-9pin-89_polysilicon-1 net-346-9pin-89_polysilicon-1--0 9.688
C14 net-346-9pin-89_polysilicon-1--0 0 0.1fF
R37 net-346-9pin-89_polysilicon-1--0 net-346-9pin-89_polysilicon-1--1 9.688
C15 net-346-9pin-89_polysilicon-1--1 0 0.1fF
R38 net-346-9pin-89_polysilicon-1--1 net-346-9pin-89_polysilicon-1--2 9.688
C16 net-346-9pin-89_polysilicon-1--2 0 0.1fF
R39 net-346-9pin-89_polysilicon-1--2 net-346-9pin-89_polysilicon-1--3 9.688
C17 net-346-9pin-89_polysilicon-1--3 0 0.1fF
R40 net-346-9pin-89_polysilicon-1--3 net-346-9pin-89_polysilicon-1--4 9.688
C18 net-346-9pin-89_polysilicon-1--4 0 0.1fF
R41 net-346-9pin-89_polysilicon-1--4 net-346-9pin-89_polysilicon-1--5 9.688
C19 net-346-9pin-89_polysilicon-1--5 0 0.1fF
R42 net-346-9pin-89_polysilicon-1--5 net-346-9pin-89_polysilicon-1--6 9.688
C20 net-346-9pin-89_polysilicon-1--6 0 0.1fF
R43 net-346-9pin-89_polysilicon-1--6 net-346-15pin-97_polysilicon-1 9.688
.ENDS Buffer
*** TOP LEVEL CELL: BufWLoad{lay}
XBufOut In Out 0 vdd InvLoad
XIn In_In In 0 vdd Buffer
** Extracted Parasitic Capacitors ***
C0 In 0 0.411fF
** Extracted Parasitic Resistors ***
** PROBE TEST ***
Cout In 0 1.2p
Vdd vdd 0 5
Vin In_In 0 Pulse (0 5 0 5p 5p 495p 1n)
*.DC Vin 0 5 0.01
.Tran 1p 5n 0 1p
.Probe
.OP
*****************************************************************************
* FET Model Parameters *
* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *
* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *
* DEV: N3740/10 * Temp= 27 *
* Modified Jan. 12, 2013 *
*****************************************************************************
.MODEL CMOSN NMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311
+ PHI = 0.7 VTO = 0.442 DELTA = 0
+ UO = 425.6466519 ETA = 0 THETA = 0.1754054
+ KP = 6.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779
+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8
+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10
+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553
+ CJSW = 5.341337E-10 MJSW = 0.5 )
.MODEL CMOSP PMOS ( LEVEL = 3
+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369
+ PHI = 0.7 VTO = -0.542 DELTA = 0
+ UO = 250 ETA = 0 THETA = 0.1573195
+ KP = 1.619415E-4 VMAX = 2.295325E5 KAPPA = 0.7448494
+ RSH = 30.0776952 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9
+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10
+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287
+ CJSW = 3.625544E-10 MJSW = 0.5 )
*****************************************************************************
.END
8. Bibliography
1. Electric VLSI Design System website, http://www.staticfreesoft.com/, [Accessed: January 12, 2013]
2. Mary Jane Irwin & Vijay Narayanan, CSE477 VLSI Digital Circuits Fall 2003, Lecture Slides, [Online]. Available:http://www.cse.psu.edu/research/mdl/mji/mjicourses/477/cse477-11speed.ppt/,
Adapted from J. Rabaey, A. Chandrakasan, & B. Nikolic, Digital Integrated Circuits, Second Ed., 2003, Prentice Hall.
3. Jim Stiles, CMOS Propagation Delay, Lecture Document, [Online].
Available: http://www.ittc.ku.edu/~jstiles/312/handouts/CMOS%20Propagation%20Delay.pdf
In figure